Difference between revisions of "GPU Driver Internals"
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===== gpu-mgr ===== | ===== gpu-mgr ===== | ||
====== vmiop ====== | |||
==== Between-VM Scheduling ==== | ==== Between-VM Scheduling ==== | ||
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===== Translation Tables ===== | ===== Translation Tables ===== | ||
====== vmiop_gva ====== | |||
== amdgpu == | == amdgpu == |
Revision as of 21:43, 9 December 2022
This page will detail the internals of various GPU drivers for use with I/O Virtualization.
i915
High Level Architecture
Scheduling
In-VM Scheduling
vExeclist
The vExeclist is a method to submit commands directly to the GPU without the use of an intermediate microcontroller.
vGuC
vGuC is a command submission interface used to process commands to the Intel Graphics Microcontroller (GuC).
Between-VM Scheduling
Memory Management
i915 Clients
Processes which make use of the Intel i915 driver receive an i915 Client ID.
Translation Tables
GTT (Graphics Translation Table)
GPU Memory on-device is a part of a GTT or Graphics Translation Table. This table stores information globally for all graphics processes within the system. Some processes access the GTT such as DRI while other's receive a Per Process Graphics Translation Table (PPGTT) buffer based on their i915 Client ID.
PPGTT (Per Process Graphics Translation Table)
Process-specific memory buffers are stored inside a Per Process Graphics Translation Table or PPGTT. This is an GPU MMU translated subregion or IOVA of global GPU memory specific to a GPU process's client ID.
Aliasing PPGTT
Real PPGTT
OpenRM
High Level Architecture
Scheduling
In-VM Scheduling
gpu-mgr
vmiop
Between-VM Scheduling
nvidia.ko
Memory Management
RM Clients
Processes which make use of the RM driver receive an RM Client ID.
Translation Tables
vmiop_gva
amdgpu
Citations (Talks and Reading Material)
- Intel Graphics Programmer's Reference Manuals (PRM)
- i915: Hardware Contexts (and some bits about batchbuffers)
- i915: The Global GTT Part 1
- i915: Aliasing PPGTT Part 2
- i915: True PPGTT Part 3
- i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
- i915: Security of the Intel Graphics Stack - Part 1 - Introduction
- i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
- i915: An Introduction to Intel GVT-g (with new architecture)