Difference between revisions of "GPU Firmware"
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| Line 14: | Line 14: | ||
Those functions are as follows: | Those functions are as follows: | ||
{| class="wikitable" | |||
- GFSP Status | |+GPU Firmware Support Package | ||
!FSP Parameter | |||
- FIVR SSC Value | !Possible Values | ||
|- | |||
- FIVR RFI Value | |GFSP Status | ||
|0x00 | |||
- GT Subsystem Vendor ID | |- | ||
|FIVR SSC Value | |||
- GT Subsystem Device ID | |*.*% | ||
|- | |||
- HDA Subsystem Vendor ID | |FIVR RFI Value | ||
|*.*MHz | |||
- HDA Subsystem Device ID | |- | ||
|GT Subsystem Vendor ID | |||
- P2SB Enable | |0x8086 | ||
|- | |||
- LMEBAR | |GT Subsystem Device ID | ||
|0x** | |||
- GTMMADDR Prefetch Capability | |- | ||
|HDA Subsystem Vendor ID | |||
- [https://open-iov.org/index.php/Merged_Drivers Display Present] | |0x0000 | ||
|- | |||
- I2C For Third Party Devices | |HDA Subsystem Device ID | ||
|0x0000 | |||
- I2C Device Address 1 | |- | ||
|P2SB Enable | |||
- I2C Device Address 2 | |Yes/No | ||
|- | |||
- I2C Bus Speed | |LMEBAR | ||
|Max | |||
|- | |||
|GTMMADDR Prefetch Capability | |||
|Prefetch Enabled | |||
|- | |||
|[https://open-iov.org/index.php/Merged_Drivers Display Present] | |||
|Enabled/Disabled | |||
|- | |||
|I2C For Third Party Devices | |||
|Enabled/Disabled | |||
|- | |||
|I2C Device Address 1 | |||
|0x0000 | |||
|- | |||
|I2C Device Address 2 | |||
|0x0000 | |||
|- | |||
|I2C Bus Speed | |||
|Standard mode (0 to 100Kbps) | |||
|} | |||
====== Editing FSP Configuration ====== | ====== Editing FSP Configuration ====== | ||
Revision as of 21:25, 18 November 2022
GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.
Intel
Firmware Images
Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. Source
Intel Firmware Support Package (FSP)
Much like CPUs Intel's GPUs also contain the FSP.
FSP Configuration
In the context of GPUs the FSP configures several functions of the device.
Those functions are as follows:
| FSP Parameter | Possible Values |
|---|---|
| GFSP Status | 0x00 |
| FIVR SSC Value | *.*% |
| FIVR RFI Value | *.*MHz |
| GT Subsystem Vendor ID | 0x8086 |
| GT Subsystem Device ID | 0x** |
| HDA Subsystem Vendor ID | 0x0000 |
| HDA Subsystem Device ID | 0x0000 |
| P2SB Enable | Yes/No |
| LMEBAR | Max |
| GTMMADDR Prefetch Capability | Prefetch Enabled |
| Display Present | Enabled/Disabled |
| I2C For Third Party Devices | Enabled/Disabled |
| I2C Device Address 1 | 0x0000 |
| I2C Device Address 2 | 0x0000 |
| I2C Bus Speed | Standard mode (0 to 100Kbps) |
Editing FSP Configuration
The FSP configuration editor can be downloaded here and it's user manual is available here.
FSP Binary Format
The FSP's binary layout is detailed within the Intel® FSP External Architecture Specification v2.4 on page 14.
Known FSP Variations
Embedded Controllers
GuC
The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's Discrete Graphics (DG*) series GPUs.