GPU Firmware - Revision history

Arthur: /* Firmware Images */

2023-04-09T17:13:39Z

Firmware Images

← Older revision		Revision as of 17:13, 9 April 2023
Line 9:		Line 9:

	=== Firmware Images ===		=== Firmware Images ===
	[[File:Screen Shot 2022-11-18 at 4.14.32 PM.png\|alt=Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification.\|thumb\|Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. [https://cdrdv2.intel.com/v1/dl/getContent/736809 Source]]]		This section will cover firmware images used in Intel GPUs.[[File:Screen Shot 2022-11-18 at 4.14.32 PM.png\|alt=Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification.\|thumb\|Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. [https://cdrdv2.intel.com/v1/dl/getContent/736809 Source]]]

	==== Intel Firmware Support Package (FSP) ====		==== Intel Firmware Support Package (FSP) ====
Line 83:		Line 83:

	=== Embedded Controllers ===		=== Embedded Controllers ===
			This section will cover firmware images as they apply to various embedded controllers within the Intel GPU.

	==== GuC ====		==== GuC ====
Line 105:		Line 106:

	=== Firmware Images ===		=== Firmware Images ===
			This section will cover firmware images used in Nvidia GPUs.

	=== Embedded Controllers ===		=== Embedded Controllers ===
			This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU.

	==== Falcon / NV-RISCV ====		==== Falcon / NV-RISCV ====

Arthur at 00:21, 2 March 2023

2023-03-02T00:21:38Z

← Older revision		Revision as of 00:21, 2 March 2023
Line 1:		Line 1:

	GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.		GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.<blockquote>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization.

			This [https://creativecommons.org/licenses/by/4.0/ CC-BY-4.0] licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation.

			Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</blockquote>

	== Intel ==		== Intel ==

Arthur at 19:24, 6 February 2023

2023-02-06T19:24:47Z

← Older revision		Revision as of 19:24, 6 February 2023
Line 152:		Line 152:
	# [https://igor-blue.github.io/2021/02/24/graphics-part2.html Security of the Intel Graphics Stack - Part 2 - FW <-> GuC]		# [https://igor-blue.github.io/2021/02/24/graphics-part2.html Security of the Intel Graphics Stack - Part 2 - FW <-> GuC]
	#[https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/ Firmware Security Realizations Part 3: SPI Write Protections]		#[https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/ Firmware Security Realizations Part 3: SPI Write Protections]
			#[https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/fsp-firmware-solutions-iot-video.html Intel® FSP: Firmware Solutions for the Internet of Things]

Arthur: /* Editing FSP Configuration */

2023-02-06T17:21:14Z

Editing FSP Configuration

← Older revision		Revision as of 17:21, 6 February 2023
Line 81:		Line 81:

	==== GuC ====		==== GuC ====
	The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's ~~Discrete Graphics~~ (DG*) series GPUs.		The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's embedded and discrete graphics (DG*) series GPUs.

	===== Hardware Architecture =====		===== Hardware Architecture =====

Arthur: /* Nvidia */

2023-01-06T00:54:52Z

Nvidia

@@ Line 104: / Line 104: @@
 === Embedded Controllers ===
-==== Falcon ====
+==== Falcon / NV-RISCV ====
-==== NvRISC ====
+==== GSP ====
-==== GSP ====
+GSP offload may occur during:
 ==== CMU ====

Arthur: /* Embedded Controllers */

2022-12-30T18:06:46Z

Embedded Controllers

← Older revision		Revision as of 18:06, 30 December 2022
Line 96:		Line 96:
	''"It runs a single process - which initializes the system and then waits for interrupts/events in a loop."''		''"It runs a single process - which initializes the system and then waits for interrupts/events in a loop."''

	====== ~~GSP~~ Blob Checksum & Code Signing ======		====== GuC Blob Checksum & Code Signing ======
	''"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing."''		''"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing."''
	== Nvidia ==		== Nvidia ==

Arthur: /* Software Architecture */

2022-12-30T17:58:26Z

Software Architecture

← Older revision		Revision as of 17:58, 30 December 2022
Line 85:		Line 85:
	===== Hardware Architecture =====		===== Hardware Architecture =====

	The following section is supported by ~~information provided via~~ [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):		''The following section is supported by [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):''

	''"The GuC - an embedded [https://www.wikiwand.com/en/I486 i486] core that supports graphics scheduling, power management and firmware attestation."''		''"The GuC - an embedded [https://www.wikiwand.com/en/I486 i486] core that supports graphics scheduling, power management and firmware attestation."''
	===== Software Architecture =====		===== Software Architecture =====

	The following section is supported by ~~information provided via~~ [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):		''The following section is supported by [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):''

	''"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services."''		''"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services."''

Arthur: /* Software Architecture */

2022-12-30T17:57:48Z

Software Architecture

← Older revision		Revision as of 17:57, 30 December 2022
Line 85:		Line 85:
	===== Hardware Architecture =====		===== Hardware Architecture =====

	~~According to~~ [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):		The following section is supported by information provided via [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):

	''"The GuC - an embedded [https://www.wikiwand.com/en/I486 i486] core that supports graphics scheduling, power management and firmware attestation."''		''"The GuC - an embedded [https://www.wikiwand.com/en/I486 i486] core that supports graphics scheduling, power management and firmware attestation."''
	===== Software Architecture =====		===== Software Architecture =====

	~~According to~~ [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):		The following section is supported by information provided via [https://igor-blue.github.io/2021/02/10/graphics-part1.html igor-blue.github.io] (see reference [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 1], [https://open-iov.org/index.php/GPU_Firmware#References_(Talks_&_Reading_Material) 2]):

	''"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services."''		''"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services."''
Line 96:		Line 96:
	''"It runs a single process - which initializes the system and then waits for interrupts/events in a loop."''		''"It runs a single process - which initializes the system and then waits for interrupts/events in a loop."''

			====== GSP Blob Checksum & Code Signing ======
	''"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing."''		''"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing."''
	== Nvidia ==		== Nvidia ==

Arthur: /* References (Talks & Reading Material) */

2022-11-23T18:57:13Z

References (Talks & Reading Material)

← Older revision		Revision as of 18:57, 23 November 2022
Line 119:		Line 119:
	# [https://igor-blue.github.io/2021/02/10/graphics-part1.html Security of the Intel Graphics Stack - Part 1 - Introduction]		# [https://igor-blue.github.io/2021/02/10/graphics-part1.html Security of the Intel Graphics Stack - Part 1 - Introduction]
	# [https://igor-blue.github.io/2021/02/24/graphics-part2.html Security of the Intel Graphics Stack - Part 2 - FW <-> GuC]		# [https://igor-blue.github.io/2021/02/24/graphics-part2.html Security of the Intel Graphics Stack - Part 2 - FW <-> GuC]
			#[https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/ Firmware Security Realizations Part 3: SPI Write Protections]

Arthur at 16:52, 23 November 2022

2022-11-23T16:52:44Z

← Older revision		Revision as of 16:52, 23 November 2022
Line 75:		Line 75:
	==== Known Firmware Package Variations ====		==== Known Firmware Package Variations ====
	Some firmware packages may include an End of Manufacturing Flash Protection Mode status of Protected or Unprotected.		Some firmware packages may include an End of Manufacturing Flash Protection Mode status of Protected or Unprotected.
			[[File:Figure 2- Firmware status information for an Intel DG2 device..png\|alt=Figure 2: Firmware status information for an Intel DG2 device.\|thumb\|Figure 2: Firmware status information for an Intel DG2 device.]]
	Similar [https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/ SPI Write Protection] functionality is made available through Intel CPUs under [[wikipedia:System_Management_Mode\|System Management Mode (SMM)]].		Similar [https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/ SPI Write Protection] functionality is made available through Intel CPUs under [[wikipedia:System_Management_Mode\|System Management Mode (SMM)]].