GPU Driver Internals - Revision history

Arthur: /* References (Talks & Reading Material) */

2023-06-19T17:53:55Z

References (Talks & Reading Material)

← Older revision		Revision as of 17:53, 19 June 2023
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	#[https://docs.nvidia.com/cuda/parallel-thread-execution/ Nvidia Parallel Thread Execution (PTX)]		#[https://docs.nvidia.com/cuda/parallel-thread-execution/ Nvidia Parallel Thread Execution (PTX)]
	#[https://blog.ffwll.ch/2013/01/i915gem-crashcourse-overview.html i915/GEM Crashcourse]		#[https://blog.ffwll.ch/2013/01/i915gem-crashcourse-overview.html i915/GEM Crashcourse]
			#[https://lwn.net/Articles/292583/ drm: Add GEM ("graphics execution manager") to i915 driver.]

Arthur: /* References (Talks & Reading Material) */

2023-06-19T17:51:34Z

References (Talks & Reading Material)

← Older revision		Revision as of 17:51, 19 June 2023
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	#[https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline Lifecycle of a Triangle - Nvidia's logical pipeline]		#[https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline Lifecycle of a Triangle - Nvidia's logical pipeline]
	#[https://docs.nvidia.com/cuda/parallel-thread-execution/ Nvidia Parallel Thread Execution (PTX)]		#[https://docs.nvidia.com/cuda/parallel-thread-execution/ Nvidia Parallel Thread Execution (PTX)]
			#[https://blog.ffwll.ch/2013/01/i915gem-crashcourse-overview.html i915/GEM Crashcourse]

Arthur: /* QEMU Host-Side Modules */

2023-06-16T20:54:27Z

QEMU Host-Side Modules

← Older revision		Revision as of 20:54, 16 June 2023
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	u-dma-buf driver allocates contiguous memory blocks in kernel as DMA buffers.		u-dma-buf driver allocates contiguous memory blocks in kernel as DMA buffers.

	====== ~~'''~~QEMU Host-Side Modules~~'''~~ ======		====== QEMU Host-Side Modules ======
	Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI.		Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI.

Arthur at 20:54, 16 June 2023

2023-06-16T20:54:13Z

@@ Line 40: / Line 40: @@
 ==== Graphics Buffer Sharing ====
 This section will cover methods provided by the GPU driver suitable for high performance graphics sharing.
 == i915 ==
 === Knowledge Resources Used ===
-This section is supported by significant contributions in open source by Zhi Wang, Ben Widawsky, and Igor Bogdanov.
+This section is supported by significant contributions to documentation and open source by '''Zhi Wang''', '''Ben Widawsky''', and '''Igor Bogdanov'''.
 See references 2, 3, 4, 5, 6, 7, 8, and 9 in the [https://open-iov.org/index.php/GPU_Driver_Internals#References_(Talks_&_Reading_Material) References (Talks & Reading Material)] section.
@@ Line 125: / Line 207: @@
 == OpenRM ==
 [[File:Figure 3- GPU BAR to Timeshared Syhededuling via Channel IO.png|alt=Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO|thumb|'''Figure 3:''' GPU BAR to Timeshared Scheduling via Channel IO.]]
 === High Level Architecture ===

Arthur: /* References (Talks & Reading Material) */

2023-05-25T20:33:37Z

References (Talks & Reading Material)

← Older revision		Revision as of 20:33, 25 May 2023
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	#[https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol05-memory_views.pdf <nowiki>i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]</nowiki>]		#[https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol05-memory_views.pdf <nowiki>i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]</nowiki>]
	#[https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline Lifecycle of a Triangle - Nvidia's logical pipeline]		#[https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline Lifecycle of a Triangle - Nvidia's logical pipeline]
			#[https://docs.nvidia.com/cuda/parallel-thread-execution/ Nvidia Parallel Thread Execution (PTX)]

Arthur: /* Translation Tables */

2023-04-05T23:29:44Z

Translation Tables

← Older revision		Revision as of 23:29, 5 April 2023
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	====== Aliasing PPGTT ======		====== Aliasing PPGTT ======
			Aliasing PPGTT (Per Process Graphics Translation Table) refers to partially separated GPU resources (process context).

	====== Real PPGTT ======		====== Real PPGTT ======
			Real PPGTT (Per Process Graphics Translation Table) refers to fully separated GPU resources (process context).

	=== Display Surface Virtualization ===		=== Display Surface Virtualization ===

Arthur: /* References (Talks & Reading Material) */

2023-04-05T23:27:44Z

References (Talks & Reading Material)

← Older revision		Revision as of 23:27, 5 April 2023
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	#[https://nehajoshi.dev/post/nvidia_mig_feature/ NVIDIA Multi-Instance GPU]		#[https://nehajoshi.dev/post/nvidia_mig_feature/ NVIDIA Multi-Instance GPU]
	#[https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol05-memory_views.pdf <nowiki>i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]</nowiki>]		#[https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol05-memory_views.pdf <nowiki>i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]</nowiki>]
			#[https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline Lifecycle of a Triangle - Nvidia's logical pipeline]

Arthur: /* Host usermode (nvidia-vgpu-mgr / libnvidiavgpu.so) */

2023-04-05T21:21:07Z

Host usermode (nvidia-vgpu-mgr / libnvidiavgpu.so)

← Older revision		Revision as of 21:21, 5 April 2023
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	The Nividia.ko kernel module exits to userspace to execute the nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin).		The Nividia.ko kernel module exits to userspace to execute the nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin).

	===== Host usermode (nvidia-vgpu-mgr / ~~libnvidiavgpu~~.so) =====		===== Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so) =====
	After exiting to userspace a daemon process (the nvidia-vgpu-mgr) and a library ~~(libnvidiavgpu~~.so).		After exiting to userspace a daemon process (the nvidia-vgpu-mgr, and it's library libnvidia-vgpu.so) are executed to schedule VM-exits described below.

	===== nvidia-vgpu-mgr =====		===== nvidia-vgpu-mgr =====
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	This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components.		This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components.

	This process and the libnvidia-vgpu.so contain, and execute the VMIOP. This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the [https://open-iov.org/index.php/GPU_Driver_Internals#RM_Core RM Core].		This process and the libnvidia-vgpu.so contain, and execute the VMIOP.

			This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the [https://open-iov.org/index.php/GPU_Driver_Internals#RM_Core RM Core].

	====== vmiop ======		====== vmiop ======

Arthur at 17:09, 5 April 2023

2023-04-05T17:09:07Z

← Older revision		Revision as of 17:09, 5 April 2023
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	This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components.		This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components.

	This process and the libnvidia-vgpu.so contain, and execute the VMIOP. This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the RM Core.		This process and the libnvidia-vgpu.so contain, and execute the VMIOP. This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the [https://open-iov.org/index.php/GPU_Driver_Internals#RM_Core RM Core].

	====== vmiop ======		====== vmiop ======

Arthur: /* RM Core */

2023-04-05T17:08:46Z

RM Core

← Older revision		Revision as of 17:08, 5 April 2023
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	==== RM Core ====		==== RM Core ====
	Core functions of the RM driver controlling resource locking, mapping, unmapping, control calls, constructors, and deconstructors.		Core functions of the RM driver controlling resource locking, mapping, unmapping, control calls, constructors, and deconstructors. Under OpenRM the RM Core runs within the GPU System Processor (GSP micro-controller) while in pre-open source versions of the Resource Manager the RM Core ran within the nvidia.ko kernel module

	=== Initialization ===		=== Initialization ===